Continued scaling of complementary metal-oxide semiconductor (CMOS) circuits presents several technical challenges. Scaling with conventional doped planar devices has become increasingly challenging. A finFET architecture offers increased scaling opportunities beyond that attainable with planar devices. See, for example, B. Yu et al., “FinFET Scaling to 10 nm Gate Length,” IEDM (2002). A finFET architecture has attractive qualities for device scaling in that no channel doping is required and also that the gate workfunction is not typically bandedge. Also, FinFET devices exhibit fast switching times and high current densities.
Do to ease of fabrication, FinFETs have been mainly produced on silicon-on-insulator (SOI) wafers. However, one potential drawback for SOI finFETs is that, for thicker fins, contacting the body node is structurally challenging. Body node contacts are needed in circuit situations where matching is critical. Also, SOI finFETs will exhibit substantial self-heating, which is a potential concern for IO drivers. On the other hand, with bulk finFETs the fins are typically continuous with the substrate, and bulk finFETs exhibit better heat-transfer properties.
Given the above-described advantages to using a finFET architecture, improved techniques for fabricating finFET devices would be desirable.